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Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
FEATURES
* 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 650MHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Output skew: 75ps (maximum) * Part-to-part skew: 300ps (maximum) * Bank skew: Bank A - 30ps (maximum) Bank B - 45ps (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature
ICS8737I-11
GENERAL DESCRIPTION
The ICS8737I-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock HiPerClockSTM Generator/Divider and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8737I-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output and part-to-part skew characteristics make the ICS8737I-11 ideal for clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
QA0 nQA0 CLK_EN D Q LE CLK nCLK PCLK nPCLK CLK_SEL MR 0 1 /1 /2 QB0 nQB0 QB1 nQB1 QA1 nQA1
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc MR VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA0 nQA0 VCC QA1 nQA1 QB0 nQB0 VCC QB1 nQB1
ICS8737I-11
20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View
8737AGI-11
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Type Description
ICS8737I-11
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 Name VEE CLK_EN CLK_SEL CLK Power Power Input Input Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input.
5 nCLK Input Pullup Inver ting differential clock input. 6 PCLK Input Pulldown Non-inver ting differential LVPECL clock input. 7 nPCLK Input Pullup Inver ting differential LVPECL clock input. 8 nc Unused No connect. 9 MR Input Pulldown Master reset. Resets the output divider. LVCMOS / LVTTL interface levels. Power Positive supply pins. 10, 13, 18 VCC 11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Outputs
ICS8737I-11
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs MR 1 0 0 0 CLK_EN X 0 0 1 CLK_SEL X 0 1 0 Selected Source X CLK, nCLK PCLK, nPCLK CLK, nCLK QA0, QA1 LOW Disabled; LOW Disabled; LOW Enabled HIGH Disabled; HIGH Disabled; HIGH Enabled nQA0, nQA1 QB0, QB1 LOW Disabled; LOW Disabled; LOW Enabled nQB0, nQB1 HIGH Disabled; HIGH Disabled; HIGH Enabled
0 1 1 PCLK, nPCLK Enabled Enabled Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
CLK_EN
nQA0, nQA1; nQB0, nQB1 QA0, QA1; QB0, QB1
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 0 1 QAx LOW HIGH LOW HIGH HIGH LOW Outputs nQAx HIGH LOW HIGH LOW LOW HIGH QBx LOW HIGH LOW HIGH HIGH LOW nQBx HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2C/W (0 lfpm) -65C to 150C
ICS8737I-11
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 55 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter CLK_EN, CLK_SEL, MR CLK_EN, CLK_SEL, MR Input High Current Input Low Current CLK_EN CLK_SEL, MR CLK_EN CLK_SEL,MR VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.3 VEE + 1.5 VCC - 1.4 VCC - 2.0 1 VCC VCC - 1.0 VCC - 1.7 0.9 Minimum Typical Maximum 150 5 Units A A A A V V V V V
ICS8737I-11
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol Parameter IIH IIL VPP VCMR VOH VOL Input High Current Input Low Current Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Bank Skew; NOTE 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 Bank A Bank B CLK, nCLK PCLK, nPCLK 650MHz 650MHz 1.2 1.1 Test Conditions Minimum Typical Maximum 650 1.8 1.7 75 30 45 300 700 700 53 Units MHz ns ns ps ps ps ps ps ps %
t sk(o) t sk(b) t sk(pp)
tR tF
odc Output Duty Cycle 47 50 All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ICS8737I-11
PARAMETER MEASUREMENT INFORMATION
V CC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -1.3V 0.135V
OUTPUT LOAD TEST CIRCUIT
VCC
nCLK, nPCLK V CLK, PCLK
PP
Cross Points
V
CMR
VEE
DIFFERENTIAL INPUT LEVEL
nQx Qx
nQy Qy
tsk(o)
OUTPUT SKEW
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8737AGI-11
REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ICS8737I-11
nQx PART 1 Qx
nQy PART 2 Qy
tsk(pp)
PART-TO-PART SKEW
80%
80% V
SWING
20% Clock Inputs and Outputs t t
20%
R
F
INPUT
AND
OUTPUT RISE
AND
FALL TIME
nCLK, nPCLK CLK, PCLK
nQA0, nQA1, nQB0, nQB1 QA0, QA1, QB0, QB1
t
PD
PROPAGATION DELAY
nQA0, nQA1, nQB0, nQB1 QA0, QA1, QB0, QB1
Pulse Width t t odc = t
PW PERIOD
PERIOD
odc & tPERIOD
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
ICS8737I-11
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50 5 2 Zo FOUT FIN Zo = 50 Zo = 50 50 50 VCC - 2V
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 5 2 Zo
FOUT
FIN
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 3A - LVPECL OUTPUT TERMINATION
8737AGI-11
RTT
Zo = 50 3 2 Zo 3 2 Zo
FIGURE 3B - LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
ICS8737I-11
This section provides information on power dissipation and junction temperature for the ICS8737I-11. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8737I-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 55mA = 190.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 120.8mW = 311.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.311W * 66.6C/W = 105.7C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA
q by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A JUNE 3, 2002
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3. Calculations and Equations.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ICS8737I-11
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4 - LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A JUNE 3, 2002
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LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
ICS8737I-11
TABLE 7. JAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8737I-11 is: 510
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ICS8737I-11
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Marking ICS8737AI-11 ICS8737AI-11 Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 72 2500 Temperature -40C to 85C -40C to 85C
ICS8737I-11
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8737AGI-11 ICS8737AGI-11T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8737AGI-11
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REV. A JUNE 3, 2002
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LOW SKEW 1/2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Added Termination for LVPECL Outputs section. Date 6/3/02
ICS8737I-11
Rev A
Table
Page 8
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